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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-07-25 10:22:43 +0300 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-07-30 12:00:03 +0300 |
| commit | 2317d018b835842df0501d8f9e9efa843068a101 (patch) | |
| tree | d6cd01662378a0c563894a764f249a0e886fe35c /tools/perf/scripts/python/syscall-counts.py | |
| parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) | |
| download | linux-2317d018b835842df0501d8f9e9efa843068a101.tar.xz | |
arm64: dts: mediatek: mt8186: Fix supported-hw mask for GPU OPPs
The speedbin eFuse reads a value 'x' from 0 to 7 and, in order to
make that compatible with opp-supported-hw, it gets post processed
as BIT(x).
Change all of the 0x30 supported-hw to 0x20 to avoid getting
duplicate OPPs for speedbin 4, and also change all of the 0x8 to
0xcf because speedbins different from 4 and 5 do support 900MHz,
950MHz, 1000MHz with the higher voltage of 850mV, 900mV, 950mV
respectively.
Fixes: f38ea593ad0d ("arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling")
Link: https://lore.kernel.org/r/20240725072243.173104-1-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions