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| author | Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> | 2022-04-29 15:58:43 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-05-04 12:22:43 +0300 |
| commit | 0017f2c856e21bb900be88469e15dac4f41f4065 (patch) | |
| tree | 732b222c5e41d0a357c384e29f385f7b0895717b /tools/perf/scripts/python/syscall-counts.py | |
| parent | 000b99e5ed1c9e33c14f3582474ae55cd739ae8d (diff) | |
| download | linux-0017f2c856e21bb900be88469e15dac4f41f4065.tar.xz | |
arm64: tegra: Add missing DFLL reset on Tegra210
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks") removed deassertion of reset lines when enabling peripheral
clocks. This breaks the initialization of the DFLL driver which relied
on this behaviour.
In order to be able to fix this, add the corresponding reset to the DT.
Tested on Google Pixel C.
Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions