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| author | Andre Przywara <andre.przywara@arm.com> | 2024-10-01 13:50:16 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2024-11-02 14:19:47 +0300 |
| commit | e0f253a52ccee3cf3eb987e99756e20c68a1aac9 (patch) | |
| tree | a4c5a3580d61f63c6047025c4f6b402a76ce2e8e /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | c7e09a613bbddd0eea086e475855aba3b2410148 (diff) | |
| download | linux-e0f253a52ccee3cf3eb987e99756e20c68a1aac9.tar.xz | |
clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.
Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.
Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions