diff options
| author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2021-04-06 02:35:37 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-04-21 04:41:12 +0300 |
| commit | 97d1765e67d61c45748deccc428ea2793983f86d (patch) | |
| tree | cd03b98be6df2a57e30c5286b2416e0aa6df2244 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 41ef8fbbef8e21e01c94105ed87b3a772b868439 (diff) | |
| download | linux-97d1765e67d61c45748deccc428ea2793983f86d.tar.xz | |
drm/amd/display: Unconditionally clear training pattern set after lt
[WHY]
While Link Training is being performed,
and the LTTPRs are in Non-LTTPR or LTTPR Transparent mode,
any DPCD registers besides those used for Link Training are not to be
accessed.
The spec defines the link training registers as DP_TRAINING_PATTERN_SET
(102h) to DP_TRAINING_LANE3_SET (106h), and DP_LANE0_1_STATUS (202h)
to DP_ADJUST_REQUEST_LANE2_3 (207h).
[HOW]
Move the current write to DPCD Address DP_LINK_TRAINING_PATTERN_SET out
of its conditional block.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions