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| author | David Abdurachmanov <david.abdurachmanov@sifive.com> | 2021-06-13 03:43:57 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-06-19 10:11:53 +0300 |
| commit | 7ede12b01b59dc67bef2e2035297dd2da5bfe427 (patch) | |
| tree | dcf04066281ea4fbbcc7db709bf462862fde2d69 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 3a02764c372c50ff7917fde5c6961f6cdb81d9d5 (diff) | |
| download | linux-7ede12b01b59dc67bef2e2035297dd2da5bfe427.tar.xz | |
riscv: dts: fu740: fix cache-controller interrupts
The order of interrupt numbers is incorrect.
The order for FU740 is: DirError, DataError, DataFail, DirFail
From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions