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authorTomasz Jeznach <tjeznach@rivosinc.com>2024-10-16 09:52:15 +0300
committerJoerg Roedel <jroedel@suse.de>2024-10-29 11:46:26 +0300
commit68682e9578fb61662a389ddeceaeb984402ed3f4 (patch)
tree9160e8a941d9a6e1735409f13dcbcd604f53f976 /tools/perf/scripts/python/syscall-counts-by-pid.py
parent5c0ebbd3c6c6e00af112fe053e81ac0c7cafe647 (diff)
downloadlinux-68682e9578fb61662a389ddeceaeb984402ed3f4.tar.xz
iommu/riscv: Add RISC-V IOMMU PCIe device driver
Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware. IOMMU hardware and system support for MSI or MSI-X is required by this implementation. Vendor and device identifiers used in this patch matches QEMU implementation of the RISC-V IOMMU PCIe device, from Rivos VID (0x1efd) range allocated by the PCI-SIG. MAINTAINERS | added iommu-pci.c already covered by matching pattern. Link: https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@ventanamicro.com/ Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/12f3bdbe519ebb7ca482191e7334d38b25b8ae8f.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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