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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2021-05-10 21:06:01 +0300 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2021-05-14 20:47:09 +0300 |
| commit | 52ae30f55a2a40cff549fac95de82f25403bd387 (patch) | |
| tree | 7d94a45d8627dfb7638aced8866a52cef572974d /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | df61cd9393845383adc4ea2410f2a91e1d1972b6 (diff) | |
| download | linux-52ae30f55a2a40cff549fac95de82f25403bd387.tar.xz | |
arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC. Add missing dma-coherent property to main_navss node.
Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.
Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@ti.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions