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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-03-06 07:08:04 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-03-28 19:16:15 +0300 |
| commit | f7d3b9277ff7eb8e84e6f8554d1c2dd78278a572 (patch) | |
| tree | e07bd2457d0a631ee6d1496b9c43514468dac84a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 0f8c7a7dd3d39fb640018b5cd977054d52c0bab2 (diff) | |
| download | linux-f7d3b9277ff7eb8e84e6f8554d1c2dd78278a572.tar.xz | |
drm/i915/vrr: Generate VRR "safe window" for DSB
Looks like TRANS_CHICKEN bit 31 means something totally different
depending on the platform:
TGL: generate VRR "safe window" for DSB
ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
So far we've only set this on ADL/DG2, but when using DSB+VRR
we also need to set it on TGL.
And a quick test on MTL says it doesn't need this bit for either
of those purposes, even though it's still documented as valid
in bspec.
Cc: stable@vger.kernel.org
Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240306040806.21697-2-ville.syrjala@linux.intel.com
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
(cherry picked from commit 810e4519a1b34b5a0ff0eab32e5b184f533c5ee9)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions