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| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-06-17 10:44:37 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-06-27 15:18:11 +0300 |
| commit | e3f4e5b1a3e654d518155b37c7b2084cbce9d1a7 (patch) | |
| tree | f320c27e02c6bed045c8812f86ed013835752c69 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6b878ac2711056dd07c712caf89f58449cf5a592 (diff) | |
| download | linux-e3f4e5b1a3e654d518155b37c7b2084cbce9d1a7.tar.xz | |
ASoC: fsl_sai: Configure dataline/FIFO information from dts property
The SAI has multiple successive FIFO registers, but in some use
case the required dataline/FIFOs are not successive, so need
get such information from dts property "fsl,dataline"
fsl,dataline has 3 values for each configuration:
first one means the type: I2S(1) or DSD(2),
second one is dataline mask for 'rx',
third one is dataline mask for 'tx'.
Also set dma peripheral address and TRCE bits according to data lane.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Link: https://lore.kernel.org/r/1655451877-16382-8-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions