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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2017-05-30 14:15:18 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-07-17 11:51:31 +0300 |
| commit | e2ab17707689c2e5bea735bc66260ecb42a81483 (patch) | |
| tree | 2d3f70cdf729d920d20d9b70af22391f71a2056b /tools/perf/scripts/python/stackcollapse.py | |
| parent | d0593c363f04ccc4bc7b6939c24a0ee65391c779 (diff) | |
| download | linux-e2ab17707689c2e5bea735bc66260ecb42a81483.tar.xz | |
pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function definitions
This patch fixes the incorrect IPSR register value definitions for
MSIOF3_{SS1,SS2}_E pin functions.
This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.
Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword, update Fixes for upstream]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions