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| author | Hrushikesh Salunke <h-salunke@ti.com> | 2025-10-17 11:46:53 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2025-11-03 12:03:59 +0300 |
| commit | cadd9234aedc9d4c5b4342f96a1ebe02314adeb2 (patch) | |
| tree | 600c5f8d3361a21579c84958a3ec81301d80d71a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 1f03b9e71e49a2f903c914f12ca5068995d916d7 (diff) | |
| download | linux-cadd9234aedc9d4c5b4342f96a1ebe02314adeb2.tar.xz | |
arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to SERDES0
J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. PCIe1
instance is used for PCIe boot process. J784S4 SoC has four instances
of 4-lane SERDES. Out of which SERDES0 is used as PHY for PCIe1. So it
needs to be functional at all stages of PCIe boot process. Thus add the
"bootph-all" boot phase tag to nodes required to enable SERDES0 at all
boot stages.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Link: https://patch.msgid.link/20251017084654.2929945-3-h-salunke@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions