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| author | Chunhao Lin <hau@realtek.com> | 2022-12-26 15:31:53 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-12-28 14:58:08 +0300 |
| commit | bb41c13c05c23d9bc46b4e37d8914078c6a40e3a (patch) | |
| tree | 2b6bd273aff03f1f3431f8d5b6bb331cec21c8d1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ad425666a1f05d9b215a84cf010c3789b2ea8206 (diff) | |
| download | linux-bb41c13c05c23d9bc46b4e37d8914078c6a40e3a.tar.xz | |
r8169: fix dmar pte write access is not set error
When close device, if wol is enabled, rx will be enabled. When open
device it will cause rx packet to be dma to the wrong memory address
after pci_set_master() and system log will show blow messages.
DMAR: DRHD: handling fault status reg 3
DMAR: [DMA Write] Request device [02:00.0] PASID ffffffff fault addr
ffdd4000 [fault reason 05] PTE Write access is not set
In this patch, driver disable tx/rx when close device. If wol is
enabled, only enable rx filter and disable rxdv_gate(if support) to
let hardware only receive packet to fifo but not to dma it.
Signed-off-by: Chunhao Lin <hau@realtek.com>
Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions