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| author | David Galiffi <David.Galiffi@amd.com> | 2020-01-30 01:02:32 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-25 19:08:19 +0300 |
| commit | b01f22ec88103d781f27aadb29277a35302db083 (patch) | |
| tree | 0ff0628b01920ff15392801ac8ac12b66be5c58f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 31cf6f35934757a6dc752e724ca529a116451b4d (diff) | |
| download | linux-b01f22ec88103d781f27aadb29277a35302db083.tar.xz | |
drm/amd/display: Workaround required for link training reliability
[Why]
A software workaround is required for all vendor-built cards on platform.
[How]
When performing DP link training, we must send TPS1 before DPCD:100h is
written with the proper bit rate value. This change must be applies in
ALL cases when LT happens.
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions