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author | Matt Roper <matthew.d.roper@intel.com> | 2022-03-02 02:15:37 +0300 |
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committer | Matt Roper <matthew.d.roper@intel.com> | 2022-03-02 17:45:16 +0300 |
commit | 944823c9463916dd53f365e9aa07f23360968080 (patch) | |
tree | 67c0e7fb332f537499ca44b42604a06ce960e393 /tools/perf/scripts/python/stackcollapse.py | |
parent | a8b2b8b06e10224c547d90ea97c483b4de511b22 (diff) | |
download | linux-944823c9463916dd53f365e9aa07f23360968080.tar.xz |
drm/i915/xehp: Define compute class and engine
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
v2:
- Add kerneldoc for drm_i915_gem_engine_class since we're adding a new
element to it. (Daniel)
- Make engine class <-> guc class converters use lookup tables to make
it more clear/explicit how the IDs map. (Tvrtko)
v3:
- Don't update uapi for now; we'll just include the driver-internal
changes for the time being.
Bspec: 46167, 45544
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-2-matthew.d.roper@intel.com
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