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| author | Raju Rangoju <Raju.Rangoju@amd.com> | 2024-09-25 16:36:40 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-09-30 02:11:53 +0300 |
| commit | 8cd9141ad4e053d361c854cc24a18a9ca050e0a1 (patch) | |
| tree | d869ba29dd5c9e0cbc11f4277a88564099cc135f /tools/perf/scripts/python/stackcollapse.py | |
| parent | efd9834b86a65f9229e90727fd61a5576c08389c (diff) | |
| download | linux-8cd9141ad4e053d361c854cc24a18a9ca050e0a1.tar.xz | |
spi: spi_amd: Updates to set tx/rx count functions
AMD SPI TX and RX counter registers are 1-byte length registers. The
existing value will be overwritten during register write, so masking is not
required.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions