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| author | Zidan Wang <zidan.wang@freescale.com> | 2015-10-26 10:19:02 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-11-16 13:06:01 +0300 |
| commit | 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645 (patch) | |
| tree | 6870e846dee1d79a83ad066ad6348aba46e7fd53 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 8005c49d9aea74d382f474ce11afbbc7d7130bec (diff) | |
| download | linux-8973112aa41b8ad956a5b47f2fe17bc2a5cf2645.tar.xz | |
ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile
ETDR and TX0~5 registers are writable and not readable. So they are non
volatile. Remove them from volatile list, and add default register value for
them.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions