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| author | Anil Varughese <aniljoy@cadence.com> | 2019-12-16 12:57:05 +0300 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 10:28:06 +0300 |
| commit | 871002d788817eb4cd0cd03101d284c3db06ed74 (patch) | |
| tree | f9d44f5def70b97d46108ebbdbcf690213bedd5a /tools/perf/scripts/python/stackcollapse.py | |
| parent | aead5fd6026d4006e494167b07a44254af8b43a9 (diff) | |
| download | linux-871002d788817eb4cd0cd03101d284c3db06ed74.tar.xz | |
phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC
The existing configuration done in Cadence Sierra driver is only for
reference and is not used in any platforms. Remove them and configure
both lane cdb and common cdb registers to be used with external
SSC configuration. This is validated in TI J721E platform.
Signed-off-by: Anil Varughese <aniljoy@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions