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| author | Martin Leung <martin.leung@amd.com> | 2020-02-12 23:38:51 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-25 19:08:35 +0300 |
| commit | 82054678aeb66907acd63df7d1d5f9556e29a5cc (patch) | |
| tree | 6b2829394a80211919696195cfeb4fd1d384b5ec /tools/perf/scripts/python/stackcollapse.py | |
| parent | dc326f61c51df641fbf4f42303e860f53ea163c1 (diff) | |
| download | linux-82054678aeb66907acd63df7d1d5f9556e29a5cc.tar.xz | |
drm/amd/display: Link training TPS1 workaround
[Why]
Previously implemented early_cr_pattern was link level but the whole
asic should be affected.
[How]
- change old link flag to dc level
- new bit in dc->work_arounds set by DM
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions