diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2017-07-12 19:55:34 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-07-17 12:01:12 +0300 |
| commit | 7aa36a334dc3f11188d9cc024cfa06debb5cf7e6 (patch) | |
| tree | 8081a705ff1f5bb2126f260748fe5ff69f69a509 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 2bf147a836918b14aae7aba2e598fa18a73e4f19 (diff) | |
| download | linux-7aa36a334dc3f11188d9cc024cfa06debb5cf7e6.tar.xz | |
pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions