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| author | Fabien Poussin <fabien.poussin@gmail.com> | 2022-11-26 22:16:36 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-11-27 00:57:50 +0300 |
| commit | 6349c162b7dc69da82d508bccf68ef017893573e (patch) | |
| tree | 1da816cfb4181626b8c0becd1ce5451e1a57afc9 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 7ebfe10ec36b80637fe746dc2371ff1d9ce71efa (diff) | |
| download | linux-6349c162b7dc69da82d508bccf68ef017893573e.tar.xz | |
pinctrl: sunxi: d1: Add CAN bus pinmuxes
The D1 pin controller contains muxes for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the pin controller
is the same across all SoC variants.
Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions