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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-06-15 11:15:58 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2024-06-19 20:14:43 +0300 |
| commit | 628e0a0118e69bed9dad14e7dbd8a8802652f5f2 (patch) | |
| tree | 43691481ba0096cb7f5a8fe61f528aff9ea9a262 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6f9323f6ad818008fc58d2f804ee4140c1b8424d (diff) | |
| download | linux-628e0a0118e69bed9dad14e7dbd8a8802652f5f2.tar.xz | |
arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support
J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
file.
Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-7-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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