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| author | Eugen Hristev <eugen.hristev@microchip.com> | 2022-06-30 12:09:26 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-07-12 13:42:37 +0300 |
| commit | 5987e6ded29d52e42fc7b06aa575c60a25eee38e (patch) | |
| tree | 87f84eadec10e73206874db63c9227196bace21a /tools/perf/scripts/python/stackcollapse.py | |
| parent | e427266460826bea21b70f9b2bb29decfb2c2620 (diff) | |
| download | linux-5987e6ded29d52e42fc7b06aa575c60a25eee38e.tar.xz | |
mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
register.
This can lead to accidental erase of certain bits in this register.
Avoid this by doing a read-modify-write operation.
Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Karl Olsen <karl@micro-technic.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220630090926.15061-1-eugen.hristev@microchip.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions