diff options
| author | Thierry Reding <treding@nvidia.com> | 2022-01-12 11:40:34 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-03-01 13:13:09 +0300 |
| commit | 28aa30b08de6f4b346f25f7c8bb5ba3739c1879c (patch) | |
| tree | 732c7af0eb157c9957ce4371ba97c5f1bd3a6842 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 025c6643a81564f066d8381b9e2f4603e0f8438f (diff) | |
| download | linux-28aa30b08de6f4b346f25f7c8bb5ba3739c1879c.tar.xz | |
drm/tegra: Fix planar formats on Tegra186 and later
Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV
register's PITCH_U field to ensure the correct value is used in all
cases. This isn't currently causing any problems because the pitch
for both U and V planes is always the same.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions