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| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2021-02-22 11:47:31 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-04-07 18:59:23 +0300 |
| commit | 213e12205232886902507ba4e2af12d79b7cbbab (patch) | |
| tree | 67f402570d02561249cac63df8c3e3705f8153c0 /tools/perf/scripts/python/stackcollapse.py | |
| parent | a38fd8748464831584a19438cbb3082b5a2dab15 (diff) | |
| download | linux-213e12205232886902507ba4e2af12d79b7cbbab.tar.xz | |
PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
Add support for routing PCIe DMA traffic coherently when
Cache Coherent Interconnect (CCI) is enabled in the system.
The "dma-coherent" property is used to determine if CCI is enabled
or not.
Refer to https://developer.arm.com/documentation/ddi0470/k/preface
for the CCI specification.
Link: https://lore.kernel.org/r/20210222084732.21521-1-bharat.kumar.gogada@xilinx.com
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions