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| author | Hsin-Yi Wang <hsinyi@chromium.org> | 2023-03-27 07:48:05 +0300 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2023-03-27 12:53:39 +0300 |
| commit | 1a2dbf0303e8793444a57a2eec0c6b29523657d9 (patch) | |
| tree | 45f29bd950d2628a492b1764fc2b2a7dc365b43a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4334aec07a62e3b1afdf54f63dca757e4ce9518c (diff) | |
| download | linux-1a2dbf0303e8793444a57a2eec0c6b29523657d9.tar.xz | |
drm/bridge: it6505: Add range and selector_reg
There are 2 banks on it6505, and when writing to different bank,
REG_BANK_SEL needs to be set to the targeted bank. The current code set
this additionally, which causes a race condition when a process is
writing bank 0 registers while another process set the bank to 1. Set
ranges in regmap config so the regmap API would handle the bank changes.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230327044804.3657551-1-hsinyi@chromium.org
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions