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| author | Rob Herring (Arm) <robh@kernel.org> | 2024-10-02 21:43:24 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2024-10-28 20:27:15 +0300 |
| commit | 0bbff9ed81654d5f06bfca484681756ee407f924 (patch) | |
| tree | 10ab083995cee3f3802c0ffa2b076dfcfa50d08a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 759b5fc6cc3e3c5841f6a3e4638b39534b0fc716 (diff) | |
| download | linux-0bbff9ed81654d5f06bfca484681756ee407f924.tar.xz | |
perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter
access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual
counters are enabled/disabled in the PMUACR_EL1 register. When UEN is
set, the CR/ER bits control EL0 write access and must be set to disable
write access.
With the access controls, the clearing of unused counters can be
skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not
need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions