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| author | Tudor Ambarus <tudor.ambarus@linaro.org> | 2025-01-15 17:18:15 +0300 |
|---|---|---|
| committer | Jassi Brar <jassisinghbrar@gmail.com> | 2025-01-19 01:18:48 +0300 |
| commit | fbf7e5ce408e0619072e84e93e875de52f2b5fa5 (patch) | |
| tree | 7a475d152ed571ae835af3d33d209f2257696844 /tools/perf/scripts/python/parallel-perf.py | |
| parent | 56cf1209f61c08cb210d993434255efcb6a907a5 (diff) | |
| download | linux-fbf7e5ce408e0619072e84e93e875de52f2b5fa5.tar.xz | |
mailbox: add Samsung Exynos driver
The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messages. When the controller is used by the
ACPM interface the shared register is ignored and the mailbox controller
acts as a doorbell. The controller just raises the interrupt to APM
after the ACPM interface has written the message to SRAM.
Add support for the Samsung Exynos mailbox controller.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions