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| author | loanchen <lo-an.chen@amd.com> | 2025-01-15 12:43:29 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-01-29 00:23:30 +0300 |
| commit | f88192d2335b5a911fcfa09338cc00624571ec5e (patch) | |
| tree | 37b70d4634bf02dcb144c72265acf9a462e1c5b2 /tools/perf/scripts/python/parallel-perf.py | |
| parent | 819bf6662b93a5a8b0c396d2c7e7fab6264c9808 (diff) | |
| download | linux-f88192d2335b5a911fcfa09338cc00624571ec5e.tar.xz | |
drm/amd/display: Correct register address in dcn35
[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Lo-An Chen <lo-an.chen@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions