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| author | Kirill A. Shutemov <kirill.shutemov@linux.intel.com> | 2024-10-15 12:58:17 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-10-20 14:07:02 +0300 |
| commit | 8e690b817e38769dc2fa0e7473e5a5dc1fc25795 (patch) | |
| tree | bbe51d126b176306c2f51dba5520354cea20a058 /tools/perf/scripts/python/parallel-perf.py | |
| parent | bc07eea2f3b330127242df2e0ec2d6cd16b4f2e8 (diff) | |
| download | linux-8e690b817e38769dc2fa0e7473e5a5dc1fc25795.tar.xz | |
x86/kvm: Override default caching mode for SEV-SNP and TDX
AMD SEV-SNP and Intel TDX have limited access to MTRR: either it is not
advertised in CPUID or it cannot be programmed (on TDX, due to #VE on
CR0.CD clear).
This results in guests using uncached mappings where it shouldn't and
pmd/pud_set_huge() failures due to non-uniform memory type reported by
mtrr_type_lookup().
Override MTRR state, making it WB by default as the kernel does for
Hyper-V guests.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Suggested-by: Binbin Wu <binbin.wu@intel.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Message-ID: <20241015095818.357915-1-kirill.shutemov@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions