diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2024-10-23 04:44:06 +0300 |
|---|---|---|
| committer | Ira Weiny <ira.weiny@intel.com> | 2024-10-26 00:07:04 +0300 |
| commit | 3a2b97b3210bd5758f66fad04c5171f85a016a04 (patch) | |
| tree | f0f9e5ec7ac3aeb98aee403ec86e3ce798fafdef /tools/perf/scripts/python/parallel-perf.py | |
| parent | 105b6235ad0f24f271aef17f8865186c4546cb3a (diff) | |
| download | linux-3a2b97b3210bd5758f66fad04c5171f85a016a04.tar.xz | |
cxl/test: Improve init-order fidelity relative to real-world systems
The investigation of an initialization failure [1] highlighted that
cxl_test does not reflect the init-order of real world systems. The
expected order is root/bus first then async probing of the memory
devices.
Fix up cxl_test to reflect that order. While it did not reproduce the
initial bug report (since that is dependent on built-in vs modular
builds), it did reveal a separate latent bug in the subsystem's decoder
shutdown flow. Fix for that sent separately.
Link: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.net [1]
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/172964784521.81806.15791069994065969243.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions