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| author | Sheetal <sheetal@nvidia.com> | 2025-05-12 08:17:39 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-05-22 13:02:05 +0300 |
| commit | 35c0d1de8e669878797e40cc625f4bdc37c3e084 (patch) | |
| tree | abeee239656b5dfe0599f32bb8010ec4c68a5725 /tools/perf/scripts/python/parallel-perf.py | |
| parent | 628dafc476eb658544ad6b5b3592bfcd82597051 (diff) | |
| download | linux-35c0d1de8e669878797e40cc625f4bdc37c3e084.tar.xz | |
ASoC: tegra: CIF: Add Tegra264 support
In Tegra264, the CIF register data bit positions are changed for I2S,
AMX, ADX and ADMAIF AHUB modules, as they now support a maximum of
32 channels. tegra264_set_cif API added to set the CIF for IPs supporting
32 channels.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-4-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions