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author | Marc Zyngier <maz@kernel.org> | 2025-02-25 20:29:18 +0300 |
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committer | Oliver Upton <oliver.upton@linux.dev> | 2025-03-04 01:54:57 +0300 |
commit | 16abeb60be621a7927d68ab77663e93f8c734f6e (patch) | |
tree | ac9fae5f65bdf99651fc049d577a71bdb7668c3c /tools/perf/scripts/python/parallel-perf.py | |
parent | b7a252e881f3322abb9ec899d13dbf7bae7d9bea (diff) | |
download | linux-16abeb60be621a7927d68ab77663e93f8c734f6e.tar.xz |
KVM: arm64: nv: Load timer before the GIC
In order for vgic_v3_load_nested to be able to observe which timer
interrupts have the HW bit set for the current context, the timers
must have been loaded in the new mode and the right timer mapped
to their corresponding HW IRQs.
At the moment, we load the GIC first, meaning that timer interrupts
injected to an L2 guest will never have the HW bit set (we see the
old configuration).
Swapping the two loads solves this particular problem.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250225172930.1850838-5-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions