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| author | William Wu <william.wu@rock-chips.com> | 2016-05-13 13:13:46 +0300 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2016-06-20 12:32:46 +0300 |
| commit | 475c8beb35e129c2f33182f476373db04008892e (patch) | |
| tree | c8ffa5787de734517d68a34d56e60f3e6c63dee7 /tools/perf/scripts/python/netdev-times.py | |
| parent | e77c561432bccf5ea9df2f49aa039c015529590e (diff) | |
| download | linux-475c8beb35e129c2f33182f476373db04008892e.tar.xz | |
usb: dwc3: add DWC3_GUCTL1 reg for debug
GUCTL1 reg has some useful functions which can be
written by user. For rockchip platform, we set
GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable
for the core is programmed to operate in 2.0 device
only) to 1 in bootrom, and after start the kernel,
we want to check whether this bit can be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions