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| author | Thierry Reding <treding@nvidia.com> | 2023-07-26 19:27:41 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2023-10-10 18:39:33 +0300 |
| commit | fd8d26ad0849519f692edc43faea8e2540c28052 (patch) | |
| tree | a48a68b88587b1b318934c6b065748ee20c792fa /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 54a195162eb6cf4dac451623dd4e19ecad9a21ea (diff) | |
| download | linux-fd8d26ad0849519f692edc43faea8e2540c28052.tar.xz | |
dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate
Some powergate definitions need more than 8 clocks, so bump the number
up to 10, which is the current maximum in any known device tree file.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions