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authorTaniya Das <tdas@codeaurora.org>2021-03-27 04:41:05 +0300
committerStephen Boyd <sboyd@kernel.org>2021-03-30 00:08:32 +0300
commite5c359f70e4b5e7b6c2bf4b0ca2d2686d543a37b (patch)
tree36c27d4bfdbcd54b0d9206f703fb572ea3c0724a /tools/perf/scripts/python/mem-phys-addr.py
parent2867b9746cef78745c594894aece6f8ef826e0b4 (diff)
downloadlinux-e5c359f70e4b5e7b6c2bf4b0ca2d2686d543a37b.tar.xz
clk: qcom: camcc: Update the clock ops for the SC7180
Some of the RCGs could be always ON from the XO source and could be used as the clock on signal for the GDSC to be operational. In the cases where the GDSCs are parked at different source with the source clock disabled, it could lead to the GDSC to be stuck at ON/OFF during gdsc disable/enable. Thus park the RCGs at XO during clock disable and update the rcg_ops to use the shared_ops. Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1616809265-11912-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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