diff options
| author | Ryan Walklin <ryan@testtoast.com> | 2024-10-23 10:56:57 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2024-10-25 17:55:10 +0300 |
| commit | d0c322b6e4bff8cc0e40ee4983bf2ab1f7f680f0 (patch) | |
| tree | 511d8892b3f677cac0e6feb2fdcc5a2908aabf82 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 9852d85ec9d492ebef56dc5f229416c925758edc (diff) | |
| download | linux-d0c322b6e4bff8cc0e40ee4983bf2ab1f7f680f0.tar.xz | |
clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
Allwinner has previously released a H616 audio driver which also
provides sigma-delta modulation for the audio PLL clocks. This approach
is used in other Allwinner SoCs, including the H3 and A64.
The manual-provided clock values are:
PLL_AUDIO(hs) = 24 MHz*N/M1
PLL_AUDIO(4X) = 24 MHz*N/M0/M1/P
PLL_AUDIO(2X) = 24 MHz*N/M0/M1/P/2
PLL_AUDIO(1X) = 24 MHz*N/M0/M1/P/4
A fixed post-divider of 2 is used to account for a M0 divider of
2, which cannot be modelled by the existing macros and ccu_nm struct.
Add SDM to the H616 clock control unit driver.
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Tested-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241023075917.186835-2-ryan@testtoast.com
[wens@csie.org: Fixed whitespace errors]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions