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authorPeter Griffin <peter.griffin@linaro.org>2024-10-31 18:00:32 +0300
committerMartin K. Petersen <martin.petersen@oracle.com>2024-11-03 04:13:02 +0300
commitcabc453ca6c3e7ff25b4f558b06ef1691a9535d3 (patch)
treee837bac9cb315d0b93112a416b09f2ead98f4d64 /tools/perf/scripts/python/mem-phys-addr.py
parentceef938bbf8b93ba3a218b4adc244cde94b582aa (diff)
downloadlinux-cabc453ca6c3e7ff25b4f558b06ef1691a9535d3.tar.xz
scsi: ufs: exynos: gs101: Enable clock gating with hibern8
Enable clock gating and hibern8 capabilities for gs101. This leads to a significantly cooler phone when running the upstream kernel. The exynos_ufs_post_hibern8() hook is also updated to remove the UIC_CMD_DME_HIBER_EXIT code path as this causes a hang on gs101. The code path is removed rather than re-factored as no other SoC in ufs-exynos driver sets UFSHCD_CAP_HIBERN8_WITH_CLK_GATING capability. Additionally until the previous commit the hibern8 callbacks were broken anyway as they expected a bool. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241031150033.3440894-14-peter.griffin@linaro.org Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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