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author | Mika Kahola <mika.kahola@intel.com> | 2025-02-18 13:00:18 +0300 |
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committer | Mika Kahola <mika.kahola@intel.com> | 2025-02-19 14:28:51 +0300 |
commit | a4ed5f3ab0ce2655a217cb214fb0603faeb64797 (patch) | |
tree | 149a77064c5d2d54b15ee8e4d9bcb71830d18da6 /tools/perf/scripts/python/mem-phys-addr.py | |
parent | c19f5a0341e0a54e61469218fd9419633db5c937 (diff) | |
download | linux-a4ed5f3ab0ce2655a217cb214fb0603faeb64797.tar.xz |
drm/i915/display: Drop crtc_state from C10/C20 pll programming
For PLL programming for C10 and C20 we don't need to
carry crtc_state but instead use only necessary parts
of the crtc_state i.e. pll_state.
This change is needed to PTL wa 14023648281 where we would
need to otherwise pass an artificial crtc_state with majority
of the struct members initialized as NULL.
v2: Use err instead of val for error handling (Imre)
Unify parameter order (Imre)
v3: Fix misplaced port_clock, and is_dp in
intel_c20_pll_program() call (Imre)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250218100019.740556-2-mika.kahola@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions