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| author | Nicolin Chen <nicolinc@nvidia.com> | 2024-11-11 06:02:26 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2024-11-12 18:09:42 +0300 |
| commit | a3799717b881aa0f4e722afb70e7b8ba84ae4f36 (patch) | |
| tree | f7bb864c34ce501129f7c749331c6ee7b49a1f8a /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 6ac7dffe7cca9b259f17b2f255b0d95ee15a76fd (diff) | |
| download | linux-a3799717b881aa0f4e722afb70e7b8ba84ae4f36.tar.xz | |
iommu/tegra241-cmdqv: Fix alignment failure at max_n_shift
When configuring a kernel with PAGE_SIZE=4KB, depending on its setting of
CONFIG_CMA_ALIGNMENT, VCMDQ_LOG2SIZE_MAX=19 could fail the alignment test
and trigger a WARN_ON:
WARNING: at drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3646
Call trace:
arm_smmu_init_one_queue+0x15c/0x210
tegra241_cmdqv_init_structures+0x114/0x338
arm_smmu_device_probe+0xb48/0x1d90
Fix it by capping max_n_shift to CMDQ_MAX_SZ_SHIFT as SMMUv3 CMDQ does.
Fixes: 918eb5c856f6 ("iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV")
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Link: https://lore.kernel.org/r/20241111030226.1940737-1-nicolinc@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions