diff options
| author | Yi Liu <yi.l.liu@intel.com> | 2024-11-08 05:13:53 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2024-11-08 16:04:50 +0300 |
| commit | 9bd008f1a91530f6b58f524f0979521161513fdd (patch) | |
| tree | 0f50c6d06c1889066e56e01fda514640709040fe /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | b45a3777ceabbe08ab7a6e97f258191c07cbab8d (diff) | |
| download | linux-9bd008f1a91530f6b58f524f0979521161513fdd.tar.xz | |
iommu/vt-d: Add a helper to flush cache for updating present pasid entry
Generalize the logic for flushing pasid-related cache upon changes to
bits other than SSADE and P which requires a different flow according
to VT-d spec.
No functional change is intended.
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Link: https://lore.kernel.org/r/20241107122234.7424-3-yi.l.liu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions