diff options
author | Dave Airlie <airlied@redhat.com> | 2025-02-21 03:50:28 +0300 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2025-02-21 03:50:29 +0300 |
commit | 9a1cd7d6df5d708ef244f93715855c8e54d79448 (patch) | |
tree | 61b1db1184b5c70d956720e5055d65d4ddad45fc /tools/perf/scripts/python/mem-phys-addr.py | |
parent | 930293b70e46dc8a3734ed4c990e4e814549e021 (diff) | |
parent | 73f69c6be2a9f22c31c775ec03c6c286bfe12cfa (diff) | |
download | linux-9a1cd7d6df5d708ef244f93715855c8e54d79448.tar.xz |
Merge tag 'drm-msm-fixes-2025-02-20' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.14-rc4
Display:
* More catalog fixes:
- to skip watchdog programming through top block if its not present
- fix the setting of WB mask to ensure the WB input control is programmed
correctly through ping-pong
- drop lm_pair for sm6150 as that chipset does not have any 3dmerge block
* Fix the mode validation logic for DP/eDP to account for widebus (2ppc)
to allow high clock resolutions
* Fix to disable dither during encoder disable as otherwise this was
causing kms_writeback failure due to resource sharing between
* WB and DSI paths as DSI uses dither but WB does not
* Fixes for virtual planes, namely to drop extraneous return and fix
uninitialized variables
* Fix to avoid spill-over of DSC encoder block bits when programming
the bits-per-component
* Fixes in the DSI PHY to protect against concurrent access of
PHY_CMN_CLK_CFG regs between clock and display drivers
Core/GPU:
* Fix non-blocking fence wait incorrectly rounding up to 1 jiffy timeout
* Only print GMU fw version once, instead of each time the GPU resumes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGtt2AODBXdod8ULXcAygf_qYvwRDVeUVtODx=2jErp6cA@mail.gmail.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions