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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-10-30 14:56:21 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-10-31 14:16:26 +0300 |
| commit | 8bffd204ded8dd52091afe6455104166c0edfed7 (patch) | |
| tree | cb932f0492dfc95718ab2fdc14cd236446462efe /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 0f0fe8497d968fef969c16f5dcff7062e85fb409 (diff) | |
| download | linux-8bffd204ded8dd52091afe6455104166c0edfed7.tar.xz | |
drm/i915/icl: Define DSI timeout registers
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit definitions
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0b943c028a05edfd61c511d712c65c7e8bf70211.1540900289.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions