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| author | Varada Pavani <v.pavani@samsung.com> | 2025-02-25 16:19:18 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-03-05 22:13:25 +0300 |
| commit | 53517a70873c7a91675f7244768aad5006cc45de (patch) | |
| tree | 1580e733ebe4aadac5e1fcffa25d40c6f3a910e8 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | f2052a4a62465c0037aef7ea7426bffdb3531e41 (diff) | |
| download | linux-53517a70873c7a91675f7244768aad5006cc45de.tar.xz | |
clk: samsung: update PLL locktime for PLL142XX used on FSD platform
Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
update PLL142XX controller locktime to 150.
Cc: stable@vger.kernel.org
Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Link: https://lore.kernel.org/r/20250225131918.50925-3-v.pavani@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions