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| author | Matt Coster <matt.coster@imgtec.com> | 2025-04-10 12:55:07 +0300 |
|---|---|---|
| committer | Matt Coster <matt.coster@imgtec.com> | 2025-04-15 14:21:51 +0300 |
| commit | 2c08b72598cc15eafbf5c9c3870e5c29e21f4827 (patch) | |
| tree | d5a9e2f0698506104dbc640e0be49f9321487f7f /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 96822d38ff574433e06a2ec0f88ebc50d44c8eaa (diff) | |
| download | linux-2c08b72598cc15eafbf5c9c3870e5c29e21f4827.tar.xz | |
drm/imagination: Remove firmware enable_reg
After a previous commit ("drm/imagination: Mask GPU IRQs in threaded
handler"), this register is now only used to enable firmware interrupts at
start-of-day. This is, however, unnecessary since they are enabled by
default.
In addition, the soon-to-be-added RISC-V firmware processors do not have
an equivalent register.
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-8-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions