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| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2021-02-22 11:47:32 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-04-07 18:59:23 +0300 |
| commit | 1c4422f22605ec0f4455400c52a31898edcda425 (patch) | |
| tree | fedc52c373794a85050d9ab8c8f5aae8c2854928 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 213e12205232886902507ba4e2af12d79b7cbbab (diff) | |
| download | linux-1c4422f22605ec0f4455400c52a31898edcda425.tar.xz | |
PCI: xilinx-nwl: Add optional "dma-coherent" property
Add optional dma-coherent property to support coherent PCIe DMA traffic.
Link: https://lore.kernel.org/r/20210222084732.21521-2-bharat.kumar.gogada@xilinx.com
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions