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| author | Marijn Suijten <marijn.suijten@somainline.org> | 2021-03-03 02:41:06 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-03-13 23:59:46 +0300 |
| commit | 0ae67123eafd056cc0e27ab27b0d3c5e4bdaf916 (patch) | |
| tree | 3e2774c604540d85171d4d9607ccdb7bc1f7a340 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | c9b86db274d229a1ab47a4e8e11fa9775fd21cbb (diff) | |
| download | linux-0ae67123eafd056cc0e27ab27b0d3c5e4bdaf916.tar.xz | |
clk: qcom: rcg2: Rectify clk_gfx3d rate rounding without mux division
In case the mux is not divided parent_req was mistakenly not assigned to
leading __clk_determine_rate to determine the best frequency setting for
a requested rate of 0, resulting in the msm8996 platform not booting.
Rectify this by refactoring the logic to unconditionally assign to
parent_req.rate with the clock rate the caller is expecting.
Fixes: 7cbb78a99db6 ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers")
Reported-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210302234106.3418665-1-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions