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author | Raag Jadav <raag.jadav@intel.com> | 2024-12-11 14:59:52 +0300 |
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committer | Andi Shyti <andi.shyti@linux.intel.com> | 2024-12-12 01:45:10 +0300 |
commit | 0937c6e7113e07a67301b809ec824b032b3821bb (patch) | |
tree | 8e99a03a88ebf62a581b5a37851b233f6a618372 /tools/perf/scripts/python/mem-phys-addr.py | |
parent | d58db10e6c38e64ea23c2911fcbe2008ef9945b9 (diff) | |
download | linux-0937c6e7113e07a67301b809ec824b032b3821bb.tar.xz |
drm/i915/dg2: Implement Wa_14022698537
G8 power state entry is disabled due to a limitation on DG2, so we
enable it from driver with Wa_14022698537. For now we enable it for
all DG2 devices with the exception of a few, for which, we enable
only when paired with whitelisted CPU models. This works with native
ASPM and reduces idle power consumption.
$ echo powersave > /sys/module/pcie_aspm/parameters/policy
$ lspci -s 0000:03:00.0 -vvv
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk-
v2: Fix Wa_ID and include it in subject (Badal)
Rephrase commit message (Jani)
v3: Move workaround to i915_pcode_init() (Badal, Anshuman)
Re-order macro (Riana)
v4: Spell fix (Riana)
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-5-raag.jadav@intel.com
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions