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author | Oliver Upton <oliver.upton@linux.dev> | 2025-03-20 00:54:32 +0300 |
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committer | Oliver Upton <oliver.upton@linux.dev> | 2025-03-20 00:54:32 +0300 |
commit | 4f2774c57a3e87e40b1cd7074e1a564847e39e4f (patch) | |
tree | 78e84318bd5141ec69d4eae22f7a860d2aa496bb /tools/perf/scripts/python/intel-pt-events.py | |
parent | 1b1d1b17b8775f58215b166e24d931890682608e (diff) | |
parent | 5980a693701229c02f19fec051ae0845309413c6 (diff) | |
download | linux-4f2774c57a3e87e40b1cd7074e1a564847e39e4f.tar.xz |
Merge branch 'kvm-arm64/writable-midr' into kvmarm/next
* kvm-arm64/writable-midr:
: Writable implementation ID registers, courtesy of Sebastian Ott
:
: Introduce a new capability that allows userspace to set the
: ID registers that identify a CPU implementation: MIDR_EL1, REVIDR_EL1,
: and AIDR_EL1. Also plug a hole in KVM's trap configuration where
: SMIDR_EL1 was readable at EL1, despite the fact that KVM does not
: support SME.
KVM: arm64: Fix documentation for KVM_CAP_ARM_WRITABLE_IMP_ID_REGS
KVM: arm64: Copy MIDR_EL1 into hyp VM when it is writable
KVM: arm64: Copy guest CTR_EL0 into hyp VM
KVM: selftests: arm64: Test writes to MIDR,REVIDR,AIDR
KVM: arm64: Allow userspace to change the implementation ID registers
KVM: arm64: Load VPIDR_EL2 with the VM's MIDR_EL1 value
KVM: arm64: Maintain per-VM copy of implementation ID regs
KVM: arm64: Set HCR_EL2.TID1 unconditionally
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
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