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author | Yash Shah <yash.shah@sifive.com> | 2020-02-20 08:15:19 +0300 |
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committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-05-21 01:05:10 +0300 |
commit | 4a3a37331248d85df9e05e9b1d8210dc5ec81f4e (patch) | |
tree | e69c611a64e0c6652aa0744119b2efd84e1baeb0 /tools/perf/scripts/python/intel-pt-events.py | |
parent | 087958a17658dcd92cdc9292e6ce4319a25198fb (diff) | |
download | linux-4a3a37331248d85df9e05e9b1d8210dc5ec81f4e.tar.xz |
riscv: Add support to determine no. of L2 cache way enabled
In order to determine the number of L2 cache ways enabled at runtime,
implement a private attribute ("number_of_ways_enabled"). Reading this
attribute returns the number of enabled L2 cache ways at runtime.
Using riscv_set_cacheinfo_ops() hook a custom function, that returns
this private attribute, to the generic ops structure which is used by
cache_get_priv_group() in cacheinfo framework.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions