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authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>2023-09-29 08:38:52 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-10-05 14:45:19 +0300
commita2b23159499efd36b2d63b3c4534075d12ddc97a (patch)
treed78a429ebe40397a0f8ab286f57c7230c7965e86 /tools/perf/scripts/python/gecko.py
parentbf51d3b2d048c312764a55d91d67a85ee5535e31 (diff)
downloadlinux-a2b23159499efd36b2d63b3c4534075d12ddc97a.tar.xz
clk: renesas: rzg2l: Fix computation formula
According to the hardware manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in the range [-32768, 32767]. Dividing k by 65536 with integer arithmetic gives zero all the time, causing slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-6-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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